Cadence Design Systems Inc. and Intel Foundry have partnered to create and validate a comprehensive advanced packaging process using Embedded Multi-die Interconnect Bridge (EMIB) technology aimed at tackling the increasing intricacies in heterogeneously integrated multi-chip(let) architectures.
Through this collaboration, Intel customers can utilize advanced packaging to expedite design processes in high-performance computing (HPC), AI, and mobile computing. The advanced EMIB flow facilitates a smooth transition for design teams, allowing them to seamlessly move from initial system-level planning, optimization, and analysis to DRC-aware implementation and physical signoff, eliminating the need for data conversion between various formats. This innovative partnership aims to substantially decrease design cycles for intricate multi-chip(let) packages.
Through their collaborative efforts, Cadence and Intel have developed an advanced packaging workflow. This includes Cadence's Allegro X APD for placement, signal/power/ground routing, in-design electrical analysis, DFM/DFA, and final manufacturing output. Additionally, it integrates Integrity 3D-IC Platform and Integrity System Planner for system-level design aggregation, planning, and optimization. The workflow also incorporates Sigrity and Clarity solvers for 3D EM extraction, two-parameter generation, early-stage and signoff signal integrity, DC/AC power analysis, and packaging model extraction. Celsius solvers are utilized for early-stage and signoff thermal signoff/stress analysis. Virtuoso Studio is employed for signal/power/ground routing of EMIB bridges, while the Pegasus Verification System ensures signoff DRC and SystemLVS.
"As more designers turn to multi-chipset architectures and advanced packaging, there's more emphasis on having the right design tools and methodologies", said Michael Jackson, Corporate Vice President of Research and Development, Custom IC and PCB Group at Cadence. "The Cadence collaboration with Intel helps streamline this transition to heterogeneous integrated solutions by offering an EMIB-certified reference flow. This optimized flow empowers our joint customers to swiftly navigate the complexities of modern electronics design in the fast-paced tech market".
"Incorporating thermal, signal integrity and power modeling early in engineering projects' planning and implementation stages is crucial for a seamless design process", said Rahul Goyal, Vice President and General Manager, Product and Design Ecosystem at Intel Foundry. "By integrating these considerations upfront, engineers can conduct concurrent design and signoff activities, which help to avert potential downstream delays. Moreover, this proactive approach confirms design viability and ensures consistent compliance with required standards and guidelines". This strategic collaboration decidedly enables the customers and reduces risks for customers engaging with Intel technology.